发明名称 |
Wide bandwidth phase-locked loop circuit |
摘要 |
A PLL circuit uses a multiple frequency range PLL in order to phase lock input signals having a wide range of frequencies. The PLL includes a VCO capable of operating in multiple different frequency ranges and a divider bank independently configurable to divide the output of the VCO. A frequency detector detects a frequency of the input signal and a frequency selector selects an appropriate frequency range for the PLL. The frequency selector automatically switches the PLL to a different frequency range as needed in response to a change in the input signal frequency. Frequency range hysteresis is implemented to avoid operating the PLL near a frequency range boundary.
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申请公布号 |
US6859509(B1) |
申请公布日期 |
2005.02.22 |
申请号 |
US20000500607 |
申请日期 |
2000.02.04 |
申请人 |
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE ADMINISTRATOR OF THE NATIONAL AERONAUTICS AND SPACE ADMINISTRATION |
发明人 |
KOUDELKA ROBERT DAVID |
分类号 |
H03L7/113;H03L7/18;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/113 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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