发明名称 DIGITAL PLL DEMODULATOR
摘要 PURPOSE:To execute the high speed of a transient response, to decrease a code waveform distortion and to stabilize a direct current reproducion by making coincident the average frequency of two reference signals and the average frequency of an FSK wave input signal and selecting the difference in the frequency of two reference signals to 1.1-1.5 times of the modulating frequency transition of the FSK wave input signal. CONSTITUTION:Oscillators 4 and 5 to function as a reference signal source respectively give the reference signal of a high frequency fH and the reference signal of a low frequency fL to a gate circuit 3. For an FSK wave input signal received by an input terminal 1, a logical calculation is executed at the section of the rectangular feeding- back signal from a frequency-dividing device 6 by an exclusive 'or' circuit 2, a phase comparing signal is outputted and given to a gate circuit 3 and an output terminal 7. The gate circuit 3, when the phase comparing signal is a high level, gives the output signal of the oscillator 4 to the frequencydividing device 6, and when the signal is a low level, gives the output signal of the oscillator 5 to the frequency-dividing device 6. The average frequency of two reference signals and the average frequency of the FSK wave input signal are made coindident and the difference in the frequency of two reference signals is selected to 1.1-1.5 times of the modulating frequency transition of the FSK wave input signal.
申请公布号 JPS62261256(A) 申请公布日期 1987.11.13
申请号 JP19860105190 申请日期 1986.05.08
申请人 YAGI ANTENNA CO LTD 发明人 KANEKO YOICHI;MORIFUJI MOTOYOSHI;KOYAMA KATSUTO
分类号 H04L27/152;H03L7/06;H04L27/14 主分类号 H04L27/152
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