| 摘要 |
A dynamic random access memory (DRAM) comprises an array of storage cells in a well 64 on a substrate, a peripheral control circuit in a second well 62, 66 on the substrate, and means for differently biasing the wells. Complementary wells may carry CMOS peripheral control circuits. A ground potential may couple the wells carrying the storage arrays thereby to minimize voltage across the storage nodes for reducing array leakage and punch-through. An on-chip back-biasing generator may couple the complementary wells carrying the peripheral control circuits to improve signal margins and electrical performance. The array wells and the peripheral circuit wells are electrically isolated from one another so that back-bias generator noise does not interfere with the storage arrays. In this fashion, the storage nodes can be grounded advantageously while simultaneously basing the peripheral circuits. <IMAGE>
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