D/A FOR CONTROLLING AN OSCILLATOR IN A PHASE LOCKED LOOP

摘要

A phase-lock-loop circuit includes a digital-to-analog converter (60, 61, 62, 63) of the bit rate multiplier type. The input word to the converter (PHER) is updated once each horizontal period (H) of a television signal. Phase information of an output signal (BRM) of the bit rate multiplier that is obtained in one horizontal period (H) is retained for affecting the phase in the immediately following horizontal period.