| 摘要 |
A lower power trim circuit in accordance with the present invention includes the series connection of a resistive element, a first transistor, and a second transistor between nodes of a voltage source. The first transistor (which is coupled to the resistive element) is much larger, e.g. twice as large, as the second transistor. When the resistive element is in a low resistance state, the first transistor dominates a node between the first and second transistors due to its large size, thereby causing the node attain a first logical state. When the resistive element is in a high resistance state, the second transistor dominates the node, causing the node to go to a second logical state. The programmable resistive element is preferably selected from a group consisting essentially of silicide resistors, capacitors, and antifuses. The low power trim circuit of the present invention consumes very little power because the gain of the transistor coupled to the resistive element is used to achieve the desired rail-to-rail swing of the output. A low power trim system of the present invention includes one or more of the aforementioned trim circuits and, in addition, a power supply, a bias generator, and a resistive network. A method for trimming a circuit includes measuring at least one resistive parameter of a resistive network in an integrated circuit, comparing the resistive parameter to a desired resistive parameter, determining a trim resistor programming pattern, and programming at least one trim resistor in the integrated circuit in accordance with the trim resistor programming pattern such that flowing a current through a series connection of the trim resistor in an unbalanced transistor pair of the integrated circuit develops a trim signal at a juncture between said unbalanced transistor pair.
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