| 摘要 |
PCT No. PCT/JP94/01481 Sec. 371 Date May 5, 1995 Sec. 102(e) Date May 5, 1995 PCT Filed Sep. 8, 1994 PCT Pub. No. WO95/08217 PCT Pub. Date Mar. 23, 1995A control circuit for a clock includes a clock multiplier having an input for receiving a clock signal, an amplifier and an output. The clock multiplier multiplies the clock signal and produces an amplified, multiplied clock signal at the output. The amplifier has a reference voltage control input for setting a value of a reference voltage in the amplifier. A peak detection circuit is provided for detecting an amplitude value of the clock signal at the input of the clock multiplier. A comparator is provided for comparing the amplitude value detected at the peak detection circuit with a further reference voltage previously set less than an amplitude value of the clock signal. A switching is coupled to the output of the comparator and to the reference voltage control input of the amplifier in the clock multiplier for switching the further reference voltage according to the output of the comparator.
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