Word line driver circuit for semiconducting memory component

摘要

The circuit has a line decoder (110) for generating a block selection signal and driving a main word line according to an address signal. A sub-word line trigger unit (120) generates a main decoding signal according to the address signal. A word decoder driver (130) buffers the main decoder signal and transfers it into a memory cell block. A block word decoder driver (140) triggers a sub-decoder signal in a corresponding block according to the block selection and main decoder signals. A sub-word line driver (150) drives a sub-word line according to the sub-decoder signal and drives the main word line via the line decoder.