The dual word line decoder includes memory cells and sub-word lines arranged in lines and columns. A sub-word line energising unit in a unitary memory cell array processes a main wordline and a sub-word line signal by an AND operation for access to a required memory cell. A first sub-word decoder for a coded address signal transmits several first sub-word line signals, while a second sub-word decoder transmits several second sub-word line signals to each sub-word line energising units in the unitary memory cell array according to the corresponding signals of the sub-word line signals.
