发明名称 EXECUTING MEMORY AREA CONTROL CIRCUIT FOR PIPELINE PROCESSING
摘要 PROBLEM TO BE SOLVED: To prevent the runaway of a microcomputer by detecting whether the execution of the present instruction of the next stage after the execution of an instruction preceding by one stage is permitted or prohibited, so as to prohibit the execution of a code in an area which is not desired originally to execute or in a data area which is not desired to be known. SOLUTION: An area signal holding circuit 2 input a present area signal 4 and holds the value as an execution are preceding by one stage. An invalid signal generation circuit 9 generates an invalid signal 12, which is activated until the next instruction is executed, by using a branching instruction executing flag signal 11 generated when a branching instruction is executed. The circuit 2 generates a latch clock by masking a clock. A reset signal decoding circuit 6 compares the signal 4 with an area signal 5 preceding by one stage in accordance with an instruction fetch access control list or decodes them to output a reset request signal 8 in the condition of prohibiting fetch access.
申请公布号 JP2000284963(A) 申请公布日期 2000.10.13
申请号 JP19990086163 申请日期 1999.03.29
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 SHIMONAGATA KATSUHIRO
分类号 G06F9/38;G06F9/32;G06F12/14;G06F21/24;(IPC1-7):G06F9/38 主分类号 G06F9/38
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