发明名称 FUKUGOSOCHI
摘要 <p>PURPOSE:To execute the error processing at decoding in a real time by using a shift means to shift a coded data one by one bit each at the occurrence of an error in a decoding circuit receiving the coded data together with a line synchronizing signal and decoding them in a real time and releasing an error signal by a line synchronizing code in the coded data. CONSTITUTION:If an error takes place, a flip-flop 107 is set and an error signal 28 goes to a high level. An output of an OR circuit 29 to a shift control circuit 24 remains at a high level. Thus, the data inputted from a storage device to a shift circuit 22 is shifted one by one bit each, the result is outputted as a code data 31. Thus, in case of an MH code, an EOL code is detected and in case of an MR code, an (EOL+1) code is detected. In case of detecting the EOL code or the like being the line synchronizing code, the compression code in succession to the line synchronizing code is taken correct and the decoding processing from the preceding line is restarted. Thus, even with an error taken place, normal decoding processing is restarted regardless of the decoding error of the preceding line.</p>
申请公布号 JP2641442(B2) 申请公布日期 1997.08.13
申请号 JP19870081272 申请日期 1987.04.03
申请人 KYANON KK 发明人 MURATA YUKIO
分类号 H03M7/40;H03M5/12;H03M7/00;H04L7/00;(IPC1-7):H04L7/00 主分类号 H03M7/40
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