Inductor Structure of Semiconductor Device and Method of Fabricating the Same

摘要

Embodiments relate to and inductor structure of a semiconductor device and a manufacturing method of the same, that may be capable of reducing a parasitic capacitance occurring between an inductor metallic interconnection and a silicon substrate. Support insulating layer patterns may be formed on a top of the silicon substrate on which the interlayer dielectric layer is formed. Inductor metallic interconnections having relatively wide widths are formed on the support insulating layer patterns. When a top protective layer covering the inductor metallic interconnections is deposited, air layers are formed under the protruding parts of the inductor metallic interconnections. Because the air layer having a lower dielectric constant may exist between the inductor metallic interconnections and the silicon substrate, a parasitic capacitance may decrease and a self-resonance frequency may increase, and may extend an available frequency band.