发明名称 TSUSHINHOHO
摘要 PURPOSE:To facilitate the circuit design and to reduce the cost by using a signal in which a 2nd level is consecutive for a time longer than 1/2 of a prescribed period at all times when lots of unit signals with a prescribed period expressing a logical value are consecutive. CONSTITUTION:Prescribed pre-stage correction is applied to a data signal received from a master station 30 by a pre-stage correction circuit 14 and the result is fed to a converter 31. A post-stage correction circuit 12 applies prescribed post-stage correction to a data signal supplied from a Schmitt circuit 34 and the result is fed to a slave station 36 and a pre-stage correction circuit 13. In this case, before a signal level changes from a 2nd level to a 1st level, the 2nd level of the signal is consecutive for a time longer than 1/2 of the prescribed period. Thus, the timing deviation time when the signal level changes from the 2nd level to the 1st level is made nearly constant and the relative deviation is small, then the signal is corrected based on the timing. Thus, jitter is easily reduced and the circuit design of the communication equipment is easy and the cost is reduced.
申请公布号 JP2646756(B2) 申请公布日期 1997.08.27
申请号 JP19890180725 申请日期 1989.07.13
申请人 SHINKO DENKI KK 发明人 OGAWA HIROSHI;TANAKA NORIHIKO
分类号 H03M5/12;H04B10/2507;H04B10/556;H04L25/49 主分类号 H03M5/12
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