High perfomance DMA controller for video processors

摘要

This invention for a VDMA will enable ultra HD resolution (4K) encode/decode at 30 frames per second. This invention maximizes interconnect/DDR utilization and reduces CPU intervention using virtual alignment, sub-tile optimization, transaction breakdown strategy, 4D indexing, a dedicated interface with the host and frame padding. The VDMA has separate buffers for non-determinative synchronous data transfers and determinative asynchronous data transfers.

主权项

1. A direct memory access unit comprising:
a descriptor interface operable to receive data processor transfer parameters corresponding to desired data transfers; a descriptor first-in-first-out memory having an input connected to said descriptor interface for receiving and storing said data processor transfer parameters and having an output; a plurality of context units operable to receive said data processor transfer parameters and control data transfer operations in accordance with said data processor transfer parameters; a breakdown and dispatch unit connected to said output of said descriptor first-in-first-out memory and to each of said plurality of context units, said breakdown and dispatch unit operable to receive said data processor transfer parameters from said descriptor first-in-first-out memory, to dispatch said data processor transfer parameters to one of said plurality of context units for control of data transfer operations; and at least one memory interface connected to each of said plurality of context units and to at least one memory for transfer of data in accordance with said data processor transfer parameters under control of one of said context units; and wherein each of said context units is operable to provide virtual alignment of data to be transferred with storage word boundaries of the at least one memory.