发明名称 Integrated circuit having reduced clock cross-talk
摘要 Charge-coupled devices are very sensitive to clock cross-talk due to the overlap between successive electrodes. The influence of this cross-talk is reduced when the clock lines are periodically connected to ground by a low-ohmic impedance. For this purpose, each clock line is controlled from a buffer, whose output is connected to a clock line. A clamping transistor is connected between the output and ground. When this clamping transistor is controlled by means of the output signal and at the same time by the input signal of the buffer, the output is clamped to ground at the instant at which the cross-talk is expected by means of only a single clamping transistor.
申请公布号 US4707844(A) 申请公布日期 1987.11.17
申请号 US19860875806 申请日期 1986.06.18
申请人 U.S. PHILIPS CORPORATION 发明人 VEENDRICK, HENDRIKUS J. M.;VAN ZANTEN, ADRIANUS T.;PFENNINGS, LEONARDUS C. M. G.
分类号 G11C27/04;G11C8/18;G11C19/28;(IPC1-7):H03K23/46;G11C7/02 主分类号 G11C27/04
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