| 摘要 |
<p>PURPOSE:To obtain a bias potential generation circuit capable of raising bias potential in a short time at the time of releasing stand-by, shortening a chip enable access time and suppressing current consumption in the state of operation. CONSTITUTION:P channel transistors P1, P2 are conducted when a chip enable signal becomes a low level. By a depression type N channel transistor N5, potential rising is accelerated when the bias potential outputted from an output node 11 is low. When the bias potential arrives at fixed voltage prescribed by the threshold value voltage of transistors P2, P3, the transistor N5 becomes non-conductive, and the current consumption in the bias potential generator is decided by only the current flowing through the depression type N channel transistor n1.</p> |
