| 摘要 |
<p>PURPOSE:To improve an access time for data by making output buffer operation an incapable state by a detection output generating at the time of switching a row line. CONSTITUTION:In an output buffer control circuit 12, when the output ENB of a row decoder output transition detection circuit 11 is an H level, an output buffer 7 is made an operation enable state by generating complementary output enable signals OTEN, -OTEN when a read enable signal RDEN is inputted. When the output ENB of the circuit 11 is an L level, the input of the signal RDEN is prohibitted, and the buffer 7 is controlled to a non-operation state. Then, no zero glitch occurs in output data for the non-operation interval of the output buffer, and the output data changes as 1 1 or 0 1. In such a manner, in the read mode of the output data in 1 1 or 0 1, even when a delay in a row selection signal due to the presence of resistance and load capacitance in the row line occurs, the occurrence of the zero glitch at the time of switching the row line is prevented, and time access for 1 data is improved.</p> |
