Logically disconnectable virtual-to-physical address translation unit and method for such disconnection

摘要

A method and structure for logically disconnecting an on-chip virtual-to-physical address translation unit from a microprocessor by holding the dynamic circuits of the translation unit in precharged state. In one embodiment, the method and structure provide a fixed remapping for the virtual address. A powering down of the translation unit effects power savings when the translation unit is not required.