| 摘要 |
<p>A field programmable device comprises: an array of processing devices; a connection matrix interconnecting the processing devices and including switches (160-163); and memory cells (24) for storing data for controlling the switches to define the configuration of the interconnections of the connection matrix. In order to provide flexible use of memory and to enable higher memory densities, gates (16g, 18g, 20g) are provided which can be used to isolate the effect of the data stored in at least one group of the memory cells and switches on the configuration of the interconnections so that the memory cells in that group are available for storing other data.</p> |
