发明名称 FREQUENCY SYNTHESIZER AND PHASE LOCKED LOOP DEVICE
摘要 PROBLEM TO BE SOLVED: To improve both a lock-up time and an S/N. SOLUTION: The phases of reference signals and internal signals outputted by a frequency divider 11 are compared in a phase comparator 11, and when a phase difference is within a prescribed range, lock detection signals are outputted from a lock detection circuit 12. When the signals are supplied to a charge pump 13, an output current is switched to be small by a changeover switch SW and the time for charging or discharging a loop filter 14 is prolonged. Thus, a noise band is narrowed and the S/N is improved. While lock-up is not performed and the lock detection signals are not supplied, the output current of the charge pump 13 is large and the lock-up time is reduced.
申请公布号 JPH11234126(A) 申请公布日期 1999.08.27
申请号 JP19980034771 申请日期 1998.02.17
申请人 TOSHIBA CORP 发明人 OMOTO TATSURO
分类号 H03L7/107;H03L7/18 主分类号 H03L7/107
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