发明名称 PAD ARRANGEMENT METHOD FOR SEMICONDUCTOR CHIP
摘要 PROBLEM TO BE SOLVED: To simultaneously measure a plurality of small pin type semiconductor chips on a wafer. SOLUTION: At both ends of one vertical side (pads 1-7) of a small pin type semiconductor chip 1, short pads (black) for pads 8 and 9, and 29 and 30 present on the other horizontal two sides facing each other are provided. At both ends of one vertical side (pads 16-22) of a small pin type semiconductor chip 1, short pads (black coated) for pads 14 and 15, and 23 and 24 present on the other horizontal two sides facing each other are provided. Thus, pads sufficient for recognizing a flash ROM storage capacity, are arranged with 11 pieces at each of vertical two sides, facing each other, of the small pin type semiconductor chip 1, 22 pieces in total. So, a plurality of succeeding small pin type semiconductor chips 1 are simultaneously measured.
申请公布号 JP2000286315(A) 申请公布日期 2000.10.13
申请号 JP19990086807 申请日期 1999.03.29
申请人 SANYO ELECTRIC CO LTD 发明人 TANITSU TSUNEHIKO
分类号 H01L27/04;G01R31/28;H01L21/66;H01L21/82;H01L21/822;(IPC1-7):H01L21/66 主分类号 H01L27/04
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