发明名称 CP FLIP-FLOP
摘要 PROBLEM TO BE SOLVED: To provide a CP flip-flop capable of operating at low power and high speed within a narrower area, in comparison with an existing flip-flop for low power and eliminating the need to additionally provide a circuit for storing latched data in the case of being used as components of system by which a circuit will not be operated by turning off a power source. SOLUTION: Delay time between a clock signal and a clock signal, with which this clock signal is delayed by a prescribed time, is sensed, input data are received within the time corresponding to the delayed time difference, and previous input data are latched until new input data are received. Thus, there is merit in that timing to store data can be designed very simply, in comparison with the conventional flip-flops.
申请公布号 JP2002158563(A) 申请公布日期 2002.05.31
申请号 JP20010296617 申请日期 2001.09.27
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 PARK KI-TAE;WON HYO-SIK
分类号 H03K3/012;H03K3/356;(IPC1-7):H03K3/356 主分类号 H03K3/012
代理机构 代理人
主权项
地址