发明名称 REFERENCE VOLTAGE GENERATING CIRCUIT FOR SEMICONDUCTOR MEMORY, AND MEMORY READ-OUT CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To suppress influence of coupling and to operate simultaneously a plurality of comparator circuits by generating a plurality of reference voltages having less temporal deviation when a plurality of sense amplifiers are operated by one reference cell. SOLUTION: This device is provided with one reference memory cell 21, a plurality of pre-sense circuit A having input terminals and output terminals connected to this reference memory cell 21, a plurality of pre-sense circuits B having a plurality of input terminals and output terminals to which output of this pre-sense circuit A are inputted, a pre-sense circuit A having an input/ output end connected to a read-out memory cell 13 side, a pre-sense circuit B having an input output end to which an out put of this pre-sense circuit A is inputted. Both outputs from the pre-sense circuit B of the reference memory cell 21 side and the pre-sense circuit B of the memory cell 13 side are made both input of a comparator circuit.</p>
申请公布号 JP2002260392(A) 申请公布日期 2002.09.13
申请号 JP20010057499 申请日期 2001.03.01
申请人 SHARP CORP 发明人 MORIKAWA YOSHINAO
分类号 G11C16/06;G11C5/14;G11C16/28;G11C16/30;(IPC1-7):G11C16/06 主分类号 G11C16/06
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