| 摘要 |
<p>A processor reduces periodic interference signal components in an input signal to obtain a desired signal. The desired signal has a predefined characteristic during an interval of time. First, an interference-representing signal (S1-S13) is stored (SWMl, Cl- Cl 3) on the basis of the input signal that occurs within the interval of time during which the desired signal has the predefined characteristic. The interference-representing signal (S1-S13) represents at least one period of a periodic interfering signal. Then, on the basis of the interference-representing signal (Sl -S 13), compensation (ICS) is repetitively provided (SWM2, SUB) for the periodic interfering signal.</p> |
| 申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V.;TRAA, WILLEBRORDUS, G.;HAANSTRA, JAN, H.;SCHAPENDONK, EDWIN |
发明人 |
TRAA, WILLEBRORDUS, G.;HAANSTRA, JAN, H.;SCHAPENDONK, EDWIN |
