| 摘要 |
An asymmetric multiprocessor capable of increasing the degree of freedom of distributed processing, minimizing the processing load on each processor (CPU), and achieving a large reduction in power consumption by reducing the operating frequency or lowering the power supply voltage. Asymmetric multiprocessor (100) includes a hardware resource mediation section (110) that mediates request signals requesting permission to use arbitrary hardware accelerators from CPU cores (101a and 101b); a signal processing content selection section (111) that selects signal processing content of dynamically reconfigurable signal processor section (107) connected as a slave; a clock skew mediation section (112) that performs control to arbitrarily shift a clock phase relationship among groups; and clock delay generation sections (113a through 113g) that delay a clock signal based on clock skew selection enable signal (114).
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