发明名称 |
Pass through debug port on a high speed asynchronous link |
摘要 |
An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.
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申请公布号 |
US7328375(B2) |
申请公布日期 |
2008.02.05 |
申请号 |
US20030749660 |
申请日期 |
2003.12.30 |
申请人 |
INTEL CORPORATION |
发明人 |
GUPTA ASHISH;FAHIM BAHAA;DICKEY KENT;JASPER JONATHAN |
分类号 |
G06F11/00;G06F7/38;G06F13/00;H04L7/04 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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