发明名称 |
VOLTAGE TOLERANT FLOATING N-WELL CIRCUIT |
摘要 |
Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state. |
申请公布号 |
WO2009018285(A3) |
申请公布日期 |
2009.03.19 |
申请号 |
WO2008US71494 |
申请日期 |
2008.07.29 |
申请人 |
QUALCOMM INCORPORATED;GUPTA, ABHEEK;SRINIVAS, VAISHNAV;MOHAN, VIVEK |
发明人 |
GUPTA, ABHEEK;SRINIVAS, VAISHNAV;MOHAN, VIVEK |
分类号 |
H03K19/003 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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