| 摘要 |
<p>PURPOSE:To draw easily a decoder pattern and to speed up the processing, by splitting an decoder output into a plurality. CONSTITUTION:An output of a NAND gate NA is received at a CMOS inverter 30, three sets n-channel MOS transistors 32 are used for pulldown, and the gates are connected to remaining 3-word line. When the NAND gate NA produces an L level output and selects word line groups W0-W3, a clock at an H level out of clocks phi00-phi11 is applied to the inverter 30, the said one inverter produces the H level output and selects one word line. A ROM cell group 40 is wired to bit lines B0, B1, B2....</p> |
