| 摘要 |
PURPOSE:To reduce the time required for a humidity resistance testing to be performed for the finished products of the titled device by a method wherein an insulating gate type element structure is provided on the circumferential part of a chip in advance, and the variation of the sheet resistance caused by the moisture infiltrated in the intrinsic gate position is measured by the presence or absence of a parasitic MOS operation which will be generated directly below the sheet resistor. CONSTITUTION:In addition to the IC chip consisting of a logic cell row 1 and an aluminum pad 2 for inner circuit, aluminum pads 3 to 5 to be used for measurement is formed at the corners of the chip in the following manner. An n<+> type drain region 8 and an n<+> source region 9 are formed diffusion on a common p type Si substrate, and said regions 8 and 9 are connected to the pads 3 and 5 provided on a field SiO2 film 7 using aluminum wirings 10 and 11. Also, a pad 4 to be used for bias voltage application is provided between the pads 3 and 5. Thus, insulating gate type elements are provided at the corner parts of the chip, a current is applied to the pad 4, and the decision whether the damp-proof property is good or not is given utilizing the variation of the threshold voltage generated at the chip. |
