| 摘要 |
A charge domain parallel processing network. The network includes a floating gate CCD tapped delay line and an array of CCD signal processors each including a charge domain digital-analog multiplier. The delay line holds and shifts analog sampled data in the form of charge packets. At each stage of the delay line a floating gate sensing electrode is coupled to an analog input of an associated one of the CCD signal processors. The sampled data in the respective delay line stages are transferred and subsequently processed in parallel in the processors. Within each processor, the computation functions are performed in the charge domain. In some forms, local charge domain accumulating memories accumulate and store the processed signals, for example, providing a matrix-matrix product network or providing a triple-matrix product network.
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