Integrated solid state memory

摘要

A modem solid memory has a matrix of memory cells (SZ) that are coupled to bit lines (BL,BL') and word lines (WL). Each pair of bit lines are coupled to a circuit (BWS) with gating transistors (TT) connected to bit line decoder circuitry (DEC). Selection of the pairs of bit lines is made using an external circuit (BWS ext) via a multiplexer (MUX). The gating stages (TT) provide for separate operation of the bit line pairs (BL,BL') such that if any error condition occurs the control circuit will not change state.