ADDER CIRCUIT ARRANGEMENT FOR ADDING OUTPUT SIGNALS FROM MAIN AND DELAYED TIME BASE GENERATORS,申请号PL19870264089-传众专利搜索

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发明名称	ADDER CIRCUIT ARRANGEMENT FOR ADDING OUTPUT SIGNALS FROM MAIN AND DELAYED TIME BASE GENERATORS
摘要
申请公布号	PL153261(B1)	申请公布日期	1991.03.29
申请号	PL19870264089	申请日期	1987.02.11
申请人		发明人
分类号	G01R;G01R13/24;G01R13/26;(IPC1-7):G01R13/26	主分类号	G01R
代理机构		代理人
主权项
地址

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