| 摘要 |
Finite impulse response (FIR) filter circuitry for processing time division multiplexed sampled signals includes parallel sets of delay elements, for delaying respective signals to be filtered, each set having a plurality of taps. Corresponding taps of the respective sets of delay elements are coupled to common weighting and summing structure. A time division multiplexed signal is coupled to the parallel sets of delay elements, respective sets being exclusively clocked on the occurrence of corresponding signals.
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