| 摘要 |
PURPOSE:To obtain an economical multiplex digital signal delay circuit by holding the 1-frame preceding data through a selector until the count value of a multi-processing type counter reaches the set value and then delivering the input signal as it is when the said count value reaches the set value. CONSTITUTION:A multiplex digital signal Ii of a multiplex degree (n) is supplied to a level change detecting circuit 1. The circuit 1 checks the level change of an input signal Ii-1 preceding the signal Ii by a frame for each channel and delivers the detection signal Vi to a multi-processing type counter 2. The count value Ai of the counter 2 obtained for each channel is compared 3 with the delay set amount D set to a comparator 3. The comparator 3 delivers the control signal Ci of a low level to a selector 4 when Ai>D is satisfied. Then the selector 4 selects the signal Ii and delivers a signal Oi. A shift register 5 supplies the signal Oi-1 delayed precedingly by a frame to the selector 4 when the signal Oi is inputted. The selector 4 keeps the signal Oi-1 and delays it until the value Ai of the counter 2 reaches the set amount D. When the value Ai reaches the amount D, the selector 4 delivers the input signal as it is. |
