| 摘要 |
<p>PROBLEM TO BE SOLVED: To easily adjust the delay of an input signal by preventing a clock derived due to a wiring delay deference from being delayed in a synchronous semiconductor integrated circuit. SOLUTION: A clock CLK is inputted to an internal clock generation circuit 44 through an input circuit 42. An output signal S44 from the circuit 44 is inputted to a driver circuit 510 through aπfilter F10 as an internal clock S51. The clock S510 becomes a trigger signal for inputting internal data S56, to be an output signal from a delay circuit 56, to an address buffer circuit 52,. The output signal S44 from the circuit 44 are inputted to a driver circuit 511 through aπfilter F11 as an internal clock S511 . The clock S511 becomes a trigger signal for inputting internal data S561 to be an output signal from a delay circuit 561 to an address buffer circuit 521 .</p> |
