| 摘要 |
PROBLEM TO BE SOLVED: To control the phase of a clock signal and to precisely take it in even if the delay time of input data fluctuates by monitoring the phase of input data in an input data take-in part taking in input data based on a clock signal from a clock generation part. SOLUTION: The clock generation part 1 forms the clock signal of n-phase and an output clock signal for data reading based on a master clock signal. A clock switching part 3 is controlled by a clock switch control part 5 and one of the clock signals of n-phase from the clock generation part 1 is switched and outputted. It is added to an input data take-in part 6 as a take-in clock signal and is added to an input data phase monitoring part 2. It monitors the phase of input data. When an error occurs by parity check, the monitoring part 2 judges that a margin is secured when the margin lacks and the error is absent and securely takes in data. |
