Synchronous graphic RAM - has delay portion in switching circuit to delay input signal separately for normal and block write for control of pre-decoder which actuates coder to select column

摘要

The synchronous graphic RAM (SGRAM) has a decoder for selecting a column line. A column pre-decoder outputs a signal for controlling the operation of the decoder. A switching portion controls the pre-decoder. The switching portion includes an input stage receiving a signal enabled during read or write operation so as to perform block write operation through the column decoder's enable pulse-width control. A delay portion variably delays the input signal separately for normal write and block write. The output signal is outputted through the delay as the column pre-decoder control signal. The delay portion may include inverters, a switching circuit (50), and two delays (51,52) for delaying the input signal for a predetermined time according to the switching portion.