发明名称 METHOD FOR LAYING OUT SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method for laying out a semiconductor integrated circuit capable of generating a circuit block common power-supply wiring whole width is automatically calculated so that it becomes maximum according to a channel width with low wiring resistance, even if the channel width of a plurality of MIS transistors constituting the circuit block is not constant. SOLUTION: By referencing to a transistor region extracted in a step S1 and a design parameter, a diffusion region is generated which is formed around the transistor region to arrange a contact for biasing a well. In a step S3, the circuit block common power-source wiring for connecting a go-around power-source wiring to a lead-in power-source wiring for each circuit is automatically generated by referencing to the diffusion region.
申请公布号 JP2002158283(A) 申请公布日期 2002.05.31
申请号 JP20000349928 申请日期 2000.11.16
申请人 NEC MICROSYSTEMS LTD 发明人 MIYAHARA SHINYA
分类号 H01L21/3205;H01L21/82;H01L21/8242;H01L23/52;H01L27/108;(IPC1-7):H01L21/82;H01L21/320;H01L21/824 主分类号 H01L21/3205
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