发明名称 |
Sequential test pattern generation using combinational techniques |
摘要 |
Test pattern generation is performed for a sequential circuit by first separating the circuit into overlapping pipelines by controlling corresponding clocks for one or more registers of the circuit so as to break feedback loops of the circuit, and then processing each of the pipelines separately in order to determine if particular target faults are detectable in the pipelines. Independent clocks may be provided for each of a number of registers of the circuit in order to facilitate the breaking of the feedback loops. The processing of the pipelines may include a first processing operation which detects target faults in a single time frame, and a second processing operation which detects target faults in two or more time frames. The first processing operation generates as many combinational test vectors as possible for each of the pipelines, while the second processing operation generates sequences of two or more combinational test vectors for each of the pipelines. Advantageously, the invention allows efficient combinational test pattern generation techniques to be applied to a sequential circuit.
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申请公布号 |
US2002112209(A1) |
申请公布日期 |
2002.08.15 |
申请号 |
US20010780861 |
申请日期 |
2001.02.09 |
申请人 |
ABRAMOVICI MIRON;YU XIAOMING |
发明人 |
ABRAMOVICI MIRON;YU XIAOMING |
分类号 |
G01R31/3183;(IPC1-7):G06F11/00;G01R31/28 |
主分类号 |
G01R31/3183 |
代理机构 |
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地址 |
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