Semiconductor memory devices having controllable input/output bit architectures and related methods

摘要

A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through N^th data bits and/or to provide first through N^th data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal. The second unit memory device may be configured to receive (N+1)^th through 2N^th data bits and/or to provide (N+1)^th through 2N^th data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal. Related methods are also discussed.