METHODS AND APPARATUS FOR MULTI-PROCESSOR PIPELINE PARALLELISM

摘要

A processor is provided which has a modular organization including at least one local store operable to store data and instructions for execution, at least one functional unit operable to execute instructions on data provided from the local store, and at least one issue logic unit operable to convert instructions provided from the local store into operations of the functional unit for executing the instructions. The at least one issue logic unit may be operable to decode a unitary instruction provided from the local store to simultaneously operate all of the functional units according to the unitary instruction. Each issue logic unit may be operable to decode multiple instructions to separately operate first and second subsets of the plurality of functional units according to respective ones of the multiple instructions.