| 摘要 |
In a PLL circuit used in a display monitor, it is made possible to design a PLL circuit using a VCO of excellent frequency stability. In this PLL circuit, low jitter of display monitor is realized without having to consider variations of oscillation frequency of VCO practically. It solves the problems of effects of variations of oscillation frequency on the cost and productivity. This PLL circuit preliminarily detects the range of frequency dividing range of the frequency dividing ratio of the dividing circuit capable of locking the PLL circuit with respect to the input signal with known frequency by frequency detecting means. The detected frequency data is stored in the memory. On the basis of the frequency data, the frequency dividing ratio of the dividing circuit is set. By this setting, even if different input signals are entered, the VCO operates at a frequency near the center of the variable range of the oscillation frequency.
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