发明名称 DIGITAL SQUELCHING CIRCUIT
摘要 PURPOSE:To eliminate unnecessary noises, by outputting a pulse signal synchronizing with a bit synchronizing signal outputted from a demodulator, from a window circuit, and switching the up-and-down operation of an up-down counting circuit. CONSTITUTION:A demodulating signal (c) from a demodulator, and a bit synchronizing signal (a) are applied to a transient detecting circuit 13 and window circuit 16, respectively. The circuit 13 converts the signal (c) to an impulse signal (d) corresponding to a variation point, and inputs it to a gate circuit 14. On the circuit 14, a threshold value is provided, and a signal (f) from the circuit 13, which has passed through said circuit is sent to an up-down counting circuit 15. When S/N of an input signal of the demodulator is high, the signal (d) synchronizes with the signal (a) and concentrates, but when S/N is low, it is distributed uniformly as shown by d', therefore, the circuit 16 sends a signal (b) which has shaped the signal (a) like a duty ratio gamma1<gamma2, to the circuit 15, and when the signal (b) is ''1'', the circuit 15 executes up-counting, and when it is ''0'', said circuit executes down-counting. The circuit 14 stops counting when the count has taken the maximum value or the minimum value, and decides whether S/N exceeds a prescribed value or not.
申请公布号 JPS5885640(A) 申请公布日期 1983.05.23
申请号 JP19810185016 申请日期 1981.11.18
申请人 MATSUSHITA DENKI SANGYO KK 发明人 HONMA KOUICHI
分类号 H04B1/10;H03G3/20 主分类号 H04B1/10
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