| 摘要 |
<p>PURPOSE:To reduce the number of testing steps for a RAM and the manufacturing cost by constituting a semiconductor integrated circuit device so that a plurality of memory devices can be concurrently selectd and the concurrent writing or reading to or from the memory device is carried out. CONSTITUTION:Buffer circuits BUFC1-2, BUFP1-4, whereby address data for executing read/write or the like of a built-in module from the outside to an inner bus in which input/output of data is done and the address is given by a CPU 3 can be supplied from the outer side, is provided. It is possible to execute read/write of data for the module from the outside directly via the above circuit. The CPU 3 is mutually connected to RAMs 1, 2 and a module selection circuit 5 or the like via an address bus 6 or a data bus 7 and the read/write is executed by means of the controlling of the CPU 3 or the outer signal. Concurrent read/write of a plurality of RAMs is executed so that it is possible to test an address decoder at the same time.</p> |
