发明名称 |
Sample hold circuit |
摘要 |
A sample and hold circuit to reduce hold error when analog data is held and transferred. The circuit includes a plurality of capacitors and inverters for guaranteeing level, selectively holds an input voltage at one capacitor by a first switching means, transfers charged voltage to a second capacitance by a second switching means and reduces data transfer time.
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申请公布号 |
US5495192(A) |
申请公布日期 |
1996.02.27 |
申请号 |
US19950487972 |
申请日期 |
1995.06.07 |
申请人 |
YOZAN INC. |
发明人 |
SHOU, GUOLIANG;YANG, WEIKANG;TAKATORI, SUNAO;YAMAMOTO, MAKOTO |
分类号 |
G11C27/02;(IPC1-7):G11C27/02 |
主分类号 |
G11C27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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