发明名称
摘要 PURPOSE:To decrease ON resistance without increasing the area of an element, by forming current paths in the direction of the thickness and the direction along the main surface of a semiconductor substrate. CONSTITUTION:The following processes are provided; buried layer, well layer for C/MOS, oxidation of source, field and gate, polycrystal silicon for gate, D-MOS source, N- and P-MOS, surface protection and wiring. In these processes, a current path in the direction from a buried layer 2 to the channel of a D-MOS FET (transversal direction) and a current path in the longitudinal direction from a drain 13 to the buried layer 2 are formed. Thereby, the cross-sectional area of current path is increased, and the resistance is reduced. As the result, the ion resistance of a D-MOS FET is decreased, and the driving capability per unit area of a transistor is increased. The current concentration on the surface hardly generates, and the reliability of element is improved.
申请公布号 JP2721155(B2) 申请公布日期 1998.03.04
申请号 JP19870034424 申请日期 1987.02.19
申请人 TOSHIBA KK 发明人 KAWAMURA TAKESHI;AKIMOTO RIEKO;SHIRAI KOJI
分类号 H01L21/331;H01L21/8234;H01L21/8249;H01L27/06;H01L29/10;H01L29/423;H01L29/73;H01L29/78 主分类号 H01L21/331
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