| 摘要 |
PROBLEM TO BE SOLVED: To surely regenerate a clock signal from a data signal with a high transmission rate. SOLUTION: A delay sum circuit 22 is provided between a signal conversion circuit 21 that converts a non-return to zero(NRZ) data signal with a bit period of T received at a data input terminal 20 into a return to zero(RZ) data signal and a self-running oscillation circuit 25 whose delay time is set to 3T/2. Every time a pulse of the RZ data signal is received from the signal conversion circuit 21, the delay sum circuit 22 gives two pulses, including the pulse to the free- running oscillation circuit 25 at an interval of a time T to allow the free-running oscillation circuit 25 to provide an output of a clock signal in synchronization with the input data signal. |
