| 摘要 |
PROBLEM TO BE SOLVED: To reduce data errors by stabilizing synchronizing operation with respect to the fluctuation of a signal level. SOLUTION: A programmable counter 16 frequency-divides the clock T0 of the even-number of times of a baud rate to generate the timing T1 of 1/2 period of the baud rate and a frequency divider 17 converts it into the timing T2 of the baud rate. A phase measuring unit 11 measures the phase changing quantity of former and later halves between the baud timing of an input π/4 shift QPSK(quadrature phase shift keying) signal (x) (amplitude limited signal a) through the use of the timing T1 with a data latch 12 and a subtracter 13 to generate the difference (d) of both of the halves and a data latch 18 makes it a difference (e) corresponding to the timing T2. A multiplier 21 gives weight to the difference (e) according to a signal level (level data f) from a level measuring device 14. An adder 19 corrects initial data (h) by the weighted difference (g) to change the frequency dividing number of the programmable counter to correct a synchronizing timing. |
