发明名称 High speed one's complement adder
摘要 A one's complement adder uses two two's complement adders, both of which are coupled to receive first and second addends at their addend inputs, however the first two's complement adder is adapted to output a first sum that is the one's complement sum that would result if no carry occurred upon addition of the first and second addends and the second two's complement adder is adapted to output a second sum that is the one's complement sum that would result if a carry did occur. A selector selects one of the first sum and the second sum as its output (and the output of the one's complement adder) based on whether or not a carry occurred. The indication of whether or not a carry occurred or not can be determined from the carry output of the first complement adder, with the first sum effected by setting the carry input for the first two's complement adder to "0" (no carry in) and the second sum effected by setting the carry input for the second two's complement adder to "1" (carry in). The selector can be a multiplexer with a select input coupled to the carry output of the first two's complement adder.
申请公布号 US6343306(B1) 申请公布日期 2002.01.29
申请号 US19990313949 申请日期 1999.05.18
申请人 SUN MICROSYSTEMS, INC. 发明人 LO JOHN
分类号 G06F7/50;G06F7/505;(IPC1-7):G06F7/50;G06F11/10 主分类号 G06F7/50
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