Clock buffer with LC circuit for jitter reduction

摘要

A clock buffer circuit utilizing an LC circuit for jitter reduction. The circuit includes a differential amplifier that is coupled to a buffer stage. The output of the buffer circuit comprises the buffer stage output. An inductor and capacitor are coupled between the buffer stage output and ground. The values of the inductor and capacitor are specified such that the resonant frequency of the LC circuit corresponds to the nominal clock frequency. The entire buffer circuit including the capacitor and inductor may be fabricated on an integrated circuit. Alternatively the capacitor and/or inductor may comprise discrete components that are coupled to the buffer stage output. Additionally, multiple capacitors and/or inductors may be fabricated on the integrated circuit to permit the resonant frequency of the LC circuit to be adjusted to match the nominal clock frequency. The capacitor(s) and/or inductor(s) on the integrated circuit may be connected to integrated circuit contacts and coupled to the buffer stage output via external connections or alternatively, via semiconductor switches.