| 摘要 |
A method for fabricating a flash memory device having a self-aligned floating gate is provided to analyze an intrinsic characteristic of a cell by forming a test transistor for analyzing a cell characteristic in a self-aligned floating gate scheme. An isolation layer(11) is formed in a semiconductor substrate(10) having a cell region and a test pattern region to define an active region, and a tunnel oxide layer is formed on the active region to form a first polysilicon layer(13) self-aligned with the isolation layer. A dielectric layer(14) and a capping polysilicon layer(15) are formed on the resultant structure. The capping polysilicon layer and the dielectric layer formed on the test pattern region are removed. A second polysilicon layer is formed on the resultant structure. The second polysilicon layer and the capping polysilicon layer formed in the cell region are etched to form a control gate by using a control gate etch mask, and the second and first polysilicon layers formed in the test pattern region are etched to form a gate of a test transistor. The dielectric layer and the first polysilicon layer in the cell region are etched to form a floating gate. The process for removing the capping polysilicon layer and the dielectric layer includes the following steps. A mask for opening the test pattern region is formed. The capping polysilicon layer and the dielectric layer are dry-etched by using the mask as an etch barrier. The mask is removed.
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